The present invention relates to a semiconductor storage device and, more particularly, to a technology effective in particular for use in an on-chip static RAM (random access memory) mounted on a large-scale logical integrated circuit device and the like. As to a static RAM in which it is arranged such that only a single latch circuit for storing information is coupled with its corresponding data line, i.e., a static RAM having a memory array of a single memory cell selection type, there is, for example, a disclosure in Japanese Provisional Publication No. 54-34726. In this patent publication, there is further proposed a method in which one of the complementary data lines is commonly owned by a pair of adjoining columns of memory cells.
The design of the memory array in the single memory cell selection type lowers power consumption but, on the other hand, there is an increase in the number of MOSFETs being used for the selection. Hence, such a memory cell array type would make it difficult to achieve a higher level of circuit integration.